[Libre-soc-dev] dcache and mmu linked up

[Luke Kenneth Casson Leighton]

On Sunday, May 2, 2021, Tobias Platen <libre-soc at platen-software.de> wrote:

> On Sun, 2021-05-02 at 11:44 +0100, Luke Kenneth Casson Leighton wrote:
> > now of course, interestingly, we have to also hack in a "no-cache"
> > bypass of all addresses [above] 0xc000_0000
>
> I guess this will have to be done in LoadStore1.


yes, like this:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/mmu/fsm.py;h=abcc06cf8963060808025afebd904d8bab1055ba;hb=HEAD#l71

one test needed is to disable the cache entirely (nc=1) so as to eliminate
it as a possible source of data corruption.

litexbios is currently calculating the wrong value.

we need much more extensive LD/ST unit tests, using the full address/data
range rather than tiny 64 byte SRAMs.

l.



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