[Libre-soc-dev] dcache and mmu linked up

[Luke Kenneth Casson Leighton]

i've managed to get the MMU and DCache linked up via PortInterfaceBase, by
getting LoadStore1 to be instantiated by the config system (just as it does
for all other memory options).  a special function id then called which
creates a link between the MMU and Dcache.

now begins the process of debugging the combination, and it's extremely
complex.

help is needed to work out what is going on.

i have added the LD/ST unit tests to soc/simple/test/test_issuer_mmu.py and
all of them should, in dcache "priv_mode" (privileged, real memory, no
virtual lookups) just "work".  no address translation.

right now that's not the case.

l.



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