[Libre-soc-dev] DCT/FFT augmentations

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Jun 28 16:19:14 BST 2021


second phase completed.  it's a bit of a mess.

the reason for passing in three registers where two could be used (one
implicitly calculated from FRA as "FRA+vl") is because there is enough
of a mess with implicit registers as it is.

also, the pipeline in this case *actually* needs to receive 3 inputs
and output 2 values.

stage 3 is REMAP but before doing that i want to actually do a mini
FFT demo (actually, DFT)

after that's done i can try doing REMAP. one thing, i am not sure if
the offset in the twin MAC should be VL or VL/2

there is a case either way, but actual demo code will help determine which.


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