[Libre-soc-dev] DCT/FFT augmentations

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Jun 25 11:08:05 BST 2021

On 6/24/21, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> when will this rabbithole hit bedrock!

not any time soon...

i have sv_analysis "fixed" however there is now a clash on names and
formats of assembler (of course, this should have been expected...)

also SVP64Asm has no understanding of the new format

    sv.lb RT, SVD(RA), RC

or more to the pount, has no underlying v3.0B to map it to.

i am therefore going to have to:

a) synthesise sv.lb (etc) by putting RC into the upper bits of D
within a v3.0B "ld RT, D(RA)"

b) add a new assembler mnemonic "ldbr" i.e. suffix all bitreversed LD

this is an interesting experiment all round, how to add new
experimental (overlapping) opcodes


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