[Libre-soc-dev] daily kan-ban update 21jun2021

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Jun 21 19:43:49 BST 2021

On 6/21/21, Tobias Platen <libre-soc at platen-software.de> wrote:
> On Mon, 2021-06-21 at 18:41 +0100, Luke Kenneth Casson Leighton wrote:
>> On 6/21/21, Tobias Platen <libre-soc at platen-software.de> wrote:
>> > today: debugging src/soc/experiment/dcache.py which fails with:
>> > Signalling ld/st error ls_error=1 mmu_error=0 cache_paradox=0
>> is this *only* dcache.py i.e. not combined with other modules? and
>> have you been able to get it down to a few clock cycles?
> No, the unit test also includes a simulated wishbone memory, the mmu
> and the load/store unit.

ok then it is unsafe to assume that the dcache.py is faulty.

> In the meanwhile I found out that the invalid
> data is loaded from the wishbone memory.

this is not a surprise, it is not designed to be pipelined but the dcache.py is.

to turn classic wishbone into "fake pipeline" you have to always
generate stall from aome certain conditions, cyc & ~ack, something
like that.

also remember, the dcache code issues address read *out of sync* with data.

all this code is horribly complex and a lot of assumptions / conditions.  sigh.


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