[Libre-soc-dev] pysvp64asm: opcode setvli not supported

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


On Tue, Jun 15, 2021 at 4:37 PM Lauri Kasanen <cand at gmx.com> wrote:

> On Tue, 15 Jun 2021 16:23:29 +0100
> Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>
> > ---
> > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> >
> >
> > On Tue, Jun 15, 2021 at 4:18 PM Lauri Kasanen <cand at gmx.com> wrote:
> >
> > >
> > > Nice that it works, but I think that there's something going wrong
> here.
> > >
> > > That last op is MLSS:
> > > for i in range(8)
> > >     sum -= fv0[i] * fv1[i]
> > >
> > > Subtraction, not add. So the neg after a mul-add loop should be there,
> > > no?
> > >
> >
> > i looked again at the c code:
> >     SUM8(MLSS, sum, w + 32, p);
> >     *samples = round_sample(&sum);
> >     *dither_state= sum;
> >
> > all i know is, it produces the right answer :)
>
> With just the first data, or all of them? That line only affects one
> result float, so only testing with one dataset is not enough.
>

ah.  right.  ok.


> Hm, that difference was in a zero. So -0, which is possible in floats,
> but should not happen in this case - there should be a test for zero,
> and fneg only done for nonzero sum.
>

can i leave that with you, i am currently doing fmadds and fmsubs.



> This is another case where the optimized ver will want the fpr-to-gpr
> move, though I need to check if the ppc comparison works for floats
> (the period after an instr).
>

i haven't added Rc=1 floats yet.  if you need them you need them.