[Libre-soc-dev] pysvp64asm: opcode setvli not supported

[Lauri Kasanen]

On Tue, 15 Jun 2021 16:01:01 +0100
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> HA! only one bit wrong!  can you tell what it is?
> https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=fd84db15aae3bdad8157f2d596d8be3f0314ddef
>
> found it...
>
> --- a/media/audio/mp3/mp3_0_apply_window_float_basicsv.s
> +++ b/media/audio/mp3/mp3_0_apply_window_float_basicsv.s
> @@ -147,7 +147,6 @@ ff_mpadsp_apply_window_float_sv:
>         # TODO sv.fmadds/mr sum, fv0.v, fv1.v
>         # sv.fmuls fv0.v, fv0.v, fv1.v
>         # sv.fadds/mr/m=r30 sum, fv0.v, sum
> -       fneg sum, sum
>
>         stfs sum, 0(out)
>
> HA!  now it's correct!

Nice that it works, but I think that there's something going wrong here.

That last op is MLSS:
for i in range(8)
    sum -= fv0[i] * fv1[i]

Subtraction, not add. So the neg after a mul-add loop should be there,
no?

- Lauri