[Libre-soc-dev] Habemus Papam.

Staf Verhaegen (FibraServi) staf at fibraservi.eu
Sat Jun 12 12:09:27 BST 2021

On 11/06/2021 22:22, Jean-Paul Chaput wrote:
> Hello All,
> My last iteration of ls180 finally produced a DRC valid design.
> I only still have to correct one minimal area violation manually.
> A very rare occurrence of bug in Track::repair(), must really iron
> out this one.
> I will work on logo insertion on next tuesday.
> I know I already asked you Staf, but can you remind me the software
> to translate an image into GDS?

I don't find back how I did, it was a tool I found by searching the net 
but I seem to have lost it. Also don't remember the name. I know I had 
to clean it up for 0.35um tape-out as single pixel intrusion violated 
the min space rule for think top metal layer.


Chips want to be free.

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