[Libre-soc-dev] Unexpected clock connexions.

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Sat Jun 5 21:24:10 BST 2021

On Sat, 2021-06-05 at 17:00 +0100, Luke Kenneth Casson Leighton wrote:
> On Sat, Jun 5, 2021 at 2:21 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> wrote:
> > 
> >   The search is unambiguous. It means 'core' instance of 'corona' model.
> >   It doesn't try to match *a* 'core' instance down the hierarchy.
> > 
> nope, not having any of it.  re-running (sigh, has to do global route takes
> 1.5 hours and then bombs out with an exception sigh)

  That is strange. I just re-cloned the soclayout repository this
  afternoon so I must be up to date. I get this signal inside the
  top level ls180.vst.
    And all the connexions looks ok.
      sys_clk --> PLL (straight from the I/O pad)
      PLL --> por_clk to all DFFs.

  I suspect some renaming that took place in Yosys or blif2vst.
  Do you have "por_clk" as a signal inside your ls180.vst ?

  The global routing should take around 5 minutes. There should
  be a misconfiguration problem somewhere.

>   Mmmm. Yes it does. 'pllclk_clk' is a signal of 'test_issuer' which
> >   is connected, in the 'ls180' model to 'por_clk'. So, as we must
> >   use the representative of net the highest in the hierarchy,
> >   'core.por_clk'.
> > 
> por_clk is in test_issuer.ti.
> l.
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