[Libre-soc-dev] Unexpected clock connexions.
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Jun 5 19:04:47 BST 2021
running cocotb test (vst, pre-PNR) on the smaller experiments10_verilog,
to which a "fake" pll has now been added, works fine.
both JTAG id and JTAG wishbone read/write.
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