[Libre-soc-dev] daily kan-ban update 02jun2021

Tobias Platen libre-soc at platen-software.de
Wed Jun 2 20:03:57 BST 2021

On Wed, 2021-06-02 at 20:36 +0200, Tobias Platen wrote:
> today: having a look on LoadStore1 and gtkwave for test_ldst_pi.py
> reading and writing to the cache works as expected if there is a TLB
> hit. On miss a TLB entry should be installed, then the data should be
> stored in the cache. But this does not work in this case.
> # failed ramdom data
> addr = 65888
> data = 0x8c5a3e460d71f0b4
> #tlb miss, takes long time to load page tables
> yield from pi_st(pi, addr, data, 8, msr_pr=1)
> yield
> #fast store of data in cache
> yield from pi_st(pi, addr, data, 8, msr_pr=1)
> yield
> #reading data from cache (fast)
> ld_data = yield from pi_ld(pi, addr, 8, msr_pr=1)
> assert(ld_data==data)
> commenting out the second store will cause the
> assertion to fail
> _______________________________________________
> Libre-soc-dev mailing list
> Libre-soc-dev at lists.libre-soc.org
> http://lists.libre-soc.org/mailman/listinfo/libre-soc-dev

I now think I have found the bug I was looking for, so I create a
bugreport soon.

# write out d data only when flag set
with m.If(self.d_w_valid):
	m.d.sync += d_out.data.eq(self.store_data)
with m.Else():
	m.d.sync += d_out.data.eq(0)

d_w_valid is only valid for a short time in the beginning of
the cycle. When there is a TLB miss, invalid data will be written to
the cache.

More information about the Libre-soc-dev mailing list