[Libre-soc-dev] synchronised incremental SV development planning

[Luke Kenneth Casson Leighton]

right.

PowerDecoder2 has the CR and INT EXTRA2/3 augmentation in place, i have a
little bit of munging to do.  SPR vectorisation i forgot about.

bit of a moment where i thought the task of generating decode_sv_rom_t
tables for microwatt would be messed up.  luckily it's doable.

explained an incremental path for Cesar so it will be easier to add SVP64
later.

next on the TODO list: setvl pseudocode, SVSTATE and other SPRs, and then
it *should* be possible to move onto ISACaller and a first unit test with a
svp64 instruction.

l.






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