[Libre-soc-dev] Simple-V svp64 draft spec

[Luke Kenneth Casson Leighton]

On Saturday, January 23, 2021, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> https://libre-soc.org/openpower/sv/implementation/

some notes:

 when 30 =>
     v.decode := decode_op_30_array(to_integer(unsigned(f_in.insn(4 downto
1))));
     v.svp64decode :=
decode_op_svp64_30_array(to_integer(unsigned(f_in.insn(4 downto 1))));

allo Paul,

thank you for saying "sure, why not" about svp64 in microwatt :)  i think
you will find it fascinating, and with the for-loop technique you deployed
for VSX it really will not be conceptually that different, you've basically
done the hard work already.

i will autogenerate an equivalent for decode1.vhdl, see above, these will
drop in at each point, in the case statements, and the data structure will
contain:

* svp64 reg augmentation is 2 or 3 bits each
* in1/2/3/out sel augmentation offset
 (and one for CR in/out, too)
* instruction is single or twin predicated.

the latter is whether there is a single src op.  extsw, LD/ST, fmv, these
are all twin-predicated.

the register augmentation, there is 9 bits available in the svp64 prefix,
so we have room for marking 3 regs with 3 bits *or* 4 regs with 2 bits.
FMAC gets 2 bits per reg for example.  popcnt gets 3.

one bit per reg in these EXTRA fields says "RT is scalar/vec" or "BA is
vector" and so on, for all regs in every instruction.

i did a comprehensive analysis of instructions, categorising them all, it's
basically just like decode_rom_t.

then with that information, when VL is set greater than 1, and any
instruction's register is marked with a "vector" bit, the for-loop
activates.

there are some prerequisite pieces that need adding, for example PC+MSR is
joined by SVSTATE and must be treated as a peer, it is after all a
Sub-Program-Counter.

that means it has to be saved and restored on exceptions.  this in turn
means a new SRR has to be allocated.  that in turn means we *need* an SPR
number allocation :)

there are quite a few little pieces like this, the implementation page
above is where i am writing them all down so that rhey can be done step by
step.

i want to make this easy and straightforward for you, if something is not
clear i will update the spec and so on until it is.

best,

l.











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