[Libre-soc-dev] synchronised incremental SV development planning

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jan 23 17:19:26 GMT 2021


https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/trans/svp64.py;hb=HEAD

this is the beginnings of a "svp64 asm-opcode to EXT001+v3.0B asm-opcode
translator".

alexandre was expecting something extremely complex, involved and
comprehensive, basically a replacement for binutils.

   this is the total opposite.

the only opcodes supported are those listed in the pseudocode mdwn files
and the CSV files.  no aliases, no segments, no fancy regname aliases:
nothing.

the sole purpose of this code is to be able to write SVP64
soc/fu/*/test_pipe_caller.py unit tests, and, explicitly: to be able to do
so *without* requiring an SV-patched version of binutils.

this does mean that we will have to translate "setvl" into a binary ".long"
format, and that's ok for now.

i am about 40% of the way through the task, having got EXTRA2/3 recognised
by reading the pseudocode mdwn files which has the register/field ordering,
e.g "cmp BA, L, RA, RB"

l.


-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


More information about the Libre-soc-dev mailing list