[Libre-soc-dev] daily kan-ban update 27dec2021

[Luke Kenneth Casson Leighton]

+        # Shift address bits 61--12 right by 0--47 bits and
+        # supply the least significant 16 bits of the result.
+        comb += addrsh.eq(r.addr[12:62] << r.shift)

another entire day spent, finding that this should be a right-shift

+        comb += addrsh.eq(r.addr[12:62] >> r.shift)

next is an invalid table entry (garbage read), checking that the
right interrupt is created (0x300) and DAR and DSISR are
set, which at the moment they are not.

l.