[Libre-soc-dev] daily kan-ban update 26dec2021

[Luke Kenneth Casson Leighton]

four days messing about and several months of code-reviews and walk-throughs
comparing mmu.py against mmu.vhdl and dcache.py against dcache.vhdl a simple
shift was missing from mmu.py

> +        # Shift address bits 61--12 right by 0--47 bits and
> +        # supply the least significant 16 bits of the result.
> +        comb += addrsh.eq(r.addr[12:62] << r.shift)
> +

now microwatt mmu.bin tests 1-3 pass: next one is a write (currently failing)
and after that is a segfault (DSISR) which causes a hang.

patiently just have to go through these all, one by one.

l.

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68