[Libre-soc-dev] [Git][vlsi-eda/coriolis][devel] 3 commits: Fix Pin managment on north & east side of the cell abutment box.

[Jean-Paul Chaput]

Hello Luke,

On Fri, 2021-12-17 at 16:38 +0000, Luke Kenneth Casson Leighton wrote:
> https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/ae1f08f039702912539b41cabd46564795b8a270
> 
> i meant to ask about something related: whether it would be sensible/sane
> to have the HDL contain the IOpad Cells already (rather than core2chip
> allocate them).
> 
> the only downside is: any HDL testing / simulation would have to be able to
> cope with tristate IO pads.
> 
> what's your thoughts, Jean-Paul?

  The use of core2chip is not mandatory. Users can perfectly supply the
  whole chip+corona+core netlists as they see fit. As long as they
  respect the pre-defined netlists organization. User may also have
  to supply the top-level positionning of the I/O pads.

    In a more general fashion, I think having a full description of
  the chip, I/O pad included can be good. So we can perform full scale
  simulations/tests. But, of course if the simulators don't support
  the pads, that may be moot...

  Best,

PS: This is our lucky day, I just got word that Gabriel Gouvine and
    our other X intern will work with us starting next March.
      We will finally get some huge brainpower to enhance Coriolis!

-- 

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