[Libre-soc-dev] [Git][vlsi-eda/coriolis][devel] 3 commits: Fix Pin managment on north & east side of the cell abutment box.

[Luke Kenneth Casson Leighton]

https://gitlab.lip6.fr/vlsi-eda/coriolis/-/commit/ae1f08f039702912539b41cabd46564795b8a270

i meant to ask about something related: whether it would be sensible/sane
to have the HDL contain the IOpad Cells already (rather than core2chip
allocate them).

the only downside is: any HDL testing / simulation would have to be able to
cope with tristate IO pads.

what's your thoughts, Jean-Paul?

l.

On Fri, Dec 17, 2021 at 4:27 PM Jean-Paul Chaput (@jpc)
<gitlab at gitlab.lip6.fr> wrote:

> * Change: In cumulus/plugins/core2chip, instead of the user providing
>     an explicit mapping towards the harness I/O pins, we expect that
>     the core block must have I/O pins with names matching thoses of
>     the harness. That way, connections are automatically made.