[Libre-soc-dev] daily kan-ban update 07dec2021

[Luke Kenneth Casson Leighton]

looking at i-cache and d-cache yesterday, there is a lot of quite detailed
conversion needed to use explicit Memory() instances (at least five possibly
seven or greater) because of assumptions in dcache.vhdl and icache.vhdl
that it would exclusively target FPGAs.

that is a hell of a lot of work so i have shelved it for now.

today i am investigating how to add in ICache at the lowest possible level
into unit tests, for testing virtual memory (mmu) instruction-load including
MMU "miss".

unfortunately the I-Cache is linked heavily into the MMU, so i am starting
with test_loadstore1.py

l.

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