[Libre-soc-dev] daily kan-ban update 03dec2021

[Tobias Platen]

On Fri, 2021-12-03 at 17:57 +0000, lkcl wrote:
> today:
> 
> fixed test_loadstore1.py and PortInterfaceBase
> 
> Tobias: a bit about gates.  gates take time to "settle".  they are
> transistors, and the voltage change (depending on input) takes time
> to literally drag itself up or down to a new output, fighting
> capacitance and resistance, all the way.
> 
> this is extremely important to remember when writing HDL and
> especially simulations.  what you had implemented was:

When I started today, I knew that I made a mistake. 
I was independetly trying out to find out where my mistake was.
That took me several hours. When I looked in gtkwave yesterday
I had no understanding. Today I think I have a better understanding.   
> 
> * clock cycle ticks
> * LD is set
> * exception occurs (alignment) on a combinatorial
>    circuit
> * Settle() was called (which is STILL NOT A CLOCK.TICK)
> * the combinatorial output was read noting the
>    exception
> (notice, no clock tick with a "yield" has yet been allowed)
> * if exception noted RESET the PortInterface
Now I have a deeper look at the fixed code. I tried to fix my broken
code causing a merge conflict. So I switched back to my email program.
> 
> whilst all the time not ever allowing one single clock tick to occur.
> 
> you had also modified PortInterfaceBase to comply with this type of
> behaviour (not letting a clock tick occur)
> 
> you MUST allow room for the hardware to have a FULL clock cycle
> between changes:
> 
> * clock tick
> * set the LD
> * CLOCK TICK
> * read the exception flag
> * if EXC happened, CLEAR the LD
> * CLOCK TICK
> * allow next operation.
> 
> l.
> 
> _______________________________________________
> Libre-soc-dev mailing list
> Libre-soc-dev at lists.libre-soc.org
> http://lists.libre-soc.org/mailman/listinfo/libre-soc-dev