[Libre-soc-dev] [RFC] SVP64 on branch instructions

[Luke Kenneth Casson Leighton]

https://libre-soc.org/openpower/isa/branch/

it occurs to me only just now that we completely forgot to evaluate
SVP64 interaction on branches, particularly when bc involves CRs.

context: i started looking at this because svstep for Vertical-First
Mode requires explicit incrementing of src/dst step, thrn a loop end
test, followed by a bc on CR0.

this is near identical to what CTR is for.

consequently, there is a case for adding a special SVP64 bc mode to
check the svstep conditions instead of CTR.

the other thing is, what does Vectorised bc mean? and what does
predicated Vectorised bc mean?

should modes be added which check *all* CR fields bring tested, or
just one, or add a bit to select either?

l.