[Libre-soc-dev] hunting around to connect up the dcache / mmu

[Luke Kenneth Casson Leighton]

On Thursday, April 29, 2021, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

>
> https://libre-soc.org/3d_gpu/mmu_dcache_links.jpg
>
> for the Minerva case, ConfigMemoryPortInterface actually establishes
> (instantiates) the entire actual instance.  it *should* be
> instantiating Loadtore1 (because that is derived from
> PortInterfaceBase).


so.  what i've done is move dcache instantiation into Loadstore1.

 now, Loadstore1, being derived from PortInterfaceBase, can go into
ConfigMemoryPortInterface, and a bit more trickery, Loadstore1 can return a
wishbone interface.

then, the MMU FSM can be set up *without* itself instantiating Loadstore1,
it can be added to it after ConfigMemoryPortInterface is created.

and that is here, in TstL0CacheBuffer:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/l0_cache.py;h=e4f02513f8449c464f43acf63d47bc5887582262;hb=HEAD#l314

which is instantiated here:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;h=f4cf959de60f9605e1f3175b1ba3a29e20c262d8;hb=HEAD#l82

HA! and that's also (next line) where the FUs incl. MMU are instantiated.

excellent.

so, a function can be added to MMU, "set_loadstore", which is called in
core.

l.




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