[Libre-soc-dev] soclayout problem

[Jean-Paul Chaput]

On Tue, 2021-04-27 at 13:52 +0100, lkcl wrote:
> not so with the SPBlock512W64B8W *because we never created a corresponding
> liberty file for it*.
> 
> if we had created a liberty file with SPBlock512W64B8W in it, this problem
> with yosys would not be happening.
> 
> the "solution" is to fool yosys to think it is not an external Cell by
> having unique names and unique model names.
> 
> hence the MODEL is spblock_0 spblock_1 spblock_2 spblock_3
> 
> it is a horrible hack, took an entire day to find the workaround.

  I have no problem using patches. I do a lot of them, including
  for my own tools. I was suspecting something like that.
  To "finish" the patch, as the SRAM block layout is a very
  heavy one (number of objects & memory footprint), I cannot
  duplicate it four time. So I will add "on the fly" in doDesign.py
  an instance of the real SPBlock in each "spblock_X".

  We are on a narrow path swerving around bugs. Hence the
  importance of freezing as soon as possible both design
  & design flow.

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