[Libre-soc-dev] soclayout problem

[lkcl]

On Tuesday, April 27, 2021, lkcl <luke.leighton at gmail.com> wrote:

>
>
>  272             # each sram is named differently (yosys blackbox issue)
>  273             for i in range(4):
>  274                 sram = DataBase.getDB().getCell(
> 'spblock512w64b8w_%i' )
>  275                 if sram:
>

 i think what is happening inside yosys is the following.

* oh, you have marked these as blackboxes? i will do as you say and call
them "external cells" as part of some library
* ah ha! but i find you have only one PLL Cell! surely this cannot be an
external cell therefore i will MAKE IT A STANDARD ONE
* ah ha! but you have multiple SPBlock512W64B8W therefore yes, i will treat
this as an external cell as part of a library
* therefore i will NOT write SPBlock512W64B8W *MODEL* into the BLIF file,
because it is an external library cell
* BUT, aiyaaaa! you have given me a liberty file which does not include
SPBlock512W64B8W!
* therefore i will BARF at you with an error, "cannot find
SPBlock512W64B8W".

you see, above, it did *not* barf about the PLL blackbox *because there is
only one* and a "model" for it is inserted into the BLIF file.

not so with the SPBlock512W64B8W *because we never created a corresponding
liberty file for it*.

if we had created a liberty file with SPBlock512W64B8W in it, this problem
with yosys would not be happening.

the "solution" is to fool yosys to think it is not an external Cell by
having unique names and unique model names.

hence the MODEL is spblock_0 spblock_1 spblock_2 spblock_3

it is a horrible hack, took an entire day to find the workaround.

l.