[Libre-soc-dev] Update on Coriolis & LS180.

[lkcl]

On Sunday, April 25, 2021, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
wrote:

>
>   At the time being, you cannot perform a "make lvx" because we don't have
>   a GDS (real) layout extractor.


ahh ok.


>
>
> > is that how FlexLib is *supposed* to work?
> >
> > i take it, you have run completed PnR "make lvx" followed by "make view"
> on say
> > experiments10_verilog/freepdk45?
>
>   No, I just made the layout.


i never see any routes, which kinda defeats the object of the exercise.


>
> This is where we have to stop (in public
>   mode) for now if we use real layout (see above).
>     You may have been mislead by the fact that AP files have been
> genarateds,
>   but they are completely wrong. I should prevent that i real mode.


i don't mind if they're wrong, as long as they are approximate (or "ghost")

as long as i can complete the PnR, which will allow me to extract the
netlist back out and then place that through cocotb i can help validate the
design.

if i cannot do that i cannot check for errors in that process before it has
to be run "for real" on the 180nm.

(it takes an insane amount of time to build the simulations post PnR)

l.