[Libre-soc-dev] Update on Coriolis & LS180.

[Jean-Paul Chaput]

On Sun, 2021-04-25 at 14:00 +0100, lkcl wrote:
> 
> 
> > ---------- Forwarded message ----------
> > From: Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> > Date: Sunday, April 25, 2021
> > Subject: Update on Coriolis & LS180.
> > To: lkcl <luke.leighton at gmail.com>
> > 
> > 
> 
>  
> > You should be able to run it now (with pinmux!)
> 
> i always, always see "iopadinout" missing.  at no time does routing begin, let alone
> complete.

  I do not run build_full.sh. I run the commands manually until "make vst".
  Then I run graphically, with "make cgt" and launch "doDesign.py" from
  the Python script menu.


> > Note that Staf hasn't integrated the display patch for diffusion layers
> > so the transistors in the standard cells look weird (hidden in fact).
> 
> because the routing cannot begin, i cannot see this, and have never been able to see
> it.
> 
> is there something missing, here?
> 
> is the FreePDK-c4m45 supposed to be imported in some way that makes it "unnecessary" to
> have AP files?

  Yes and no... The PDK Master (either for TSMC or FreePDK45) do not need the
  AP files. In fact, the standard cells layout are generated by Python scripts
  (through calls to "setup()") and *not* loaded from files.

  At the time being, you cannot perform a "make lvx" because we don't have
  a GDS (real) layout extractor. cougar works on symbolic layout only (AP files)
  that we don't have when working in real mode.
    Of course, at LIP6 we do that with commercial tools, so we can perform
  the various checks.
    This can be a call for project though : developping an efficient real
  layout extractor. I think Matthias Koeferlein (KLayout) is not far from
  that.
    So you cannot mix real generation layout with symbolic extraction.
    
  You're trying to fit a square pole in a round hole with a hammer 8-) .


> is that how FlexLib is *supposed* to work?
> 
> i take it, you have run completed PnR "make lvx" followed by "make view" on say
> experiments10_verilog/freepdk45?

  No, I just made the layout. This is where we have to stop (in public
  mode) for now if we use real layout (see above).
    You may have been mislead by the fact that AP files have been genarateds,
  but they are completely wrong. I should prevent that i real mode.

-- 

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