[Libre-soc-dev] ls180 update

[whygee at f-cpu.org]

On 2021-04-16 16:04, Luke Kenneth Casson Leighton wrote:
> quick update:
> 
> * marie-minerve of lip6.fr has tagle running on an extracted netlist 
> from a
> small test, it does transistor level static timing analysis.  with that
> passing the next thing to try is ls180
> https://www-soc.lip6.fr/equipe-cian/logiciels/tasyagle/
> 
> * staf has run SPICE and other DRC on the 4K SRAM block, it passed
> simulations.
> 
> * i have been doing JTAG ghdl cocotb simulations of pre and post 
> layout,
> with a small test, this created a series of errors which Jean-Paul has
> fixed.  the post pnr wishbone test takes several seconds to complete: 
> it
> will be quite fascinating (scary) to run the full ls180.
> 
> l.

Amazing !