[Libre-soc-dev] cxxsim with jtag connections

[Luke Kenneth Casson Leighton]

On Friday, April 9, 2021, Richard Wilbur <richard.wilbur at gmail.com> wrote:

>
>
> Awesome!!
>
> Now the onus is on us to create a great testsuite with good coverage and
> the depth required to catch errors ideally before we send the design to the
> foundry


the upload program is here:


https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;hb=HEAD

it is quite obvious where the assembly listing goes


there is 512 bytes at address 0x0 and 256 bytes at address 0x700 as DFFs.
16k SRAM if it works starts at 0x1000.

if we are really lucky the sdram interface works, meaning that Winbond 16
mbyte 133mhz SDRAM ICs can be wired up.

also a litex UART and a 1 bit SPI master, I2C, 3 EINTs and 16 GPIO.




>
> —but at least (and most importantly for our reputation) before we send
> chips to customers!


well as a test ASIC there will be only maybe 20 working.


>
> Three cheers for the test infrastructure!


:)

well, at the moment the output from BLIF and conversion to VHDL through
coriolis2 blif2vst.py is a million line verilog file when imported back
through the yosys plugin.

trying to run yosys "flatten" on that is going into a black hole of CPU
time on the multiplier.

given that 64 bit mul is 12,000 gates this should not be a huge surprise.

compiling the cxxsim module may take several days.

l.



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