[Libre-soc-dev] WIP demo of deficiency of 6600-derived architecture compared to register renaming

[Jacob Lifshay]

On Tue, Oct 27, 2020, 14:24 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

>
> 1) "Notice how the WaR Waits on `r9` cause 2 instructions to finish
> per cycle (5 micro-ops per 2 cycles)
>
> right.  this isn't necessarily the case.  once an FU has read from the
> regfile into its in-flight it drops the dependency entirely.  thus if
> the new instruction being issued is after that point there will only
> be the one WaR wait, not two.
>

Those aren't caused by instructions needing to read the value (those are
all taken care of by forwarding), but instead by the limit that each
register can only write once per clock and because there is no mechanism to
drop earlier writes when a later write is known to occur (and not be
shadowed).

>
> 2) in column 3 i'm not seeing an INT reg write.  so the delay "Av r3"
> is unnecessary.
>

That's caused by waiting for the associated memory read to finish before
writing the ldu's address register, otherwise a sigsegv could cause the
corruption of the register's previous value.

Jacob