[Libre-soc-dev] WIP demo of deficiency of 6600-derived architecture compared to register renaming

[Jacob Lifshay]

I think I found a performance deficiency where the 6600-derived
architecture has a bottleneck in the speed it can write to the
register file when one register is repeatedly written -- it's limited
to 1 write per clock, yet register renaming (since the writes are to
different registers due to renaming) can support more than 1 write per
clock cycle. This is assuming that the 6600-derived architecture can
forward values without needing to go through the register file
(forwarding buses), otherwise it is waay slower.

I spent several hours coming up with a demo to show this, but ended up
running out of time today. The partially finished demo:
https://libre-soc.org/3d_gpu/architecture/compared_to_register_renaming/

Also, we should find a better markdown renderer, the above page looks
waay better using VSCode's builtin markdown preview.

Jacob