[Libre-soc-dev] silicon catalyst starting in canada

[whygee at f-cpu.org]

On 2020-10-17 06:17, Cole Poirier wrote:
> Apologies I misspoke in my previous email. I meant I think it’s worth
> seeing if it’s relevant or useful to us.

I'll try to apply Luke's principles here, and I see that Google
barely knows a thing about this method. So it's totally uncharted 
territory,
it's even feeling speculative to me and would create more troubles for 
probably
no meaningful benefit, until this approach is widely integrated in
mainstream EDA tools. Which might not happen before many years, if ever.

> I posted it here because I have no
> understanding of this area so needed help interpreting it. If you say 
> it’s
> weird and you don’t understand it, it may not be relevant. Thanks for 
> your
> help Yann! If you have more to say about it I’d be interested in 
> hearing
> it. I’m here to learn.

I learn too !

The SRAM bit patent does not seem interesting.
The relevant bit seems to be the other patent with the 3-bits decoder
where each select bit is driven by a separate rail.

The question is "is it scaleable below 180 nm" and I believe
that Jean-Paul Chaput and Staf have a much better perspective.
 From the little I know, I suspect that dealing with multiple
rails could create breakdown issues at the transistor level because
the gates can't stand more than 1V. Using higher differentials,
even when a trace runs nearby, could create all sorts of delicate
problems.

Anyway this makes me curious... Multi-rail systems are an interesting
enhancement strategy, for example in class-D amplifiers where efficiency
is critical. So there could be some potential to save "some energy",
maybe 50%, at the cost of EDA complexity (at least).

> Cole
yg