[Libre-soc-dev] daily kan-ban update 15oct2020

[Cole Poirier]

On Fri, Oct 16, 2020 at 2:41 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Fri, Oct 16, 2020 at 10:37 PM Cole Poirier <colepoirier at gmail.com> wrote:
>
> > Will do, running pywriter.py now, then will run issuer_verilog.py,
> > then will test the fpga load with --sys-clk-freq=55.
>
> fpga build you mean.

Is the following sequence correct?

./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55
./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --build
./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --load

Cole