[Libre-soc-dev] daily kan-ban update 15oct2020

[Cole Poirier]

On Thu, Oct 15, 2020 at 10:28 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> ahh at frickin last.  it was the dummy PLL that i'd added, with clock
> re-routing, not properly connected up.  gaah.  ok so we have "working
> FPGA of current master" after i added a bypass mechanism of the PLL
> when building verilog.

Grrr!! But also, woohooo!! To clarify, this affects the coriolis P&R?
Because I was able to run ./versa_ecp5.py --load --fpga ulx3s85f
yesterday and it successfully programmed my fpga. In other words, I am
as usual confused.

Yesterday I got started with debugging JTAG that's currently inverting
the inputs. Mostly just reading through the files and trying to get a
sense of how they all work together.

Just reported two separate bugs for defining JTAG pins in our fpga's,
one per variant since I figure any crossover here would be disastrous.

Was there one other JTAG related task that we talked about? I've been
trying to remember since yesterday and it's really bugging me.

Cole