[Libre-soc-dev] daily kan-ban update 12oct2020

[Cole Poirier]

Today:

created litex/florent/ulx3s85f.py based on
lites/florent/versa_ecp5.py, successfully completes when run as
`./ulx3s85f.py`, `./ulx3s85f.py --build`, and loads to my 85K LUT
ULX3S FPGA when run as `./ulx3s85f.py --load` :)

What should I do now? Try sending commands over JTAG, openocd, gdb?

Now, going to work on adding getopt to all of the currently hard-coded
options in simple/issuer_verilog.py etc, making sure to test that it
still works with this augmentation.

Cole