[Libre-soc-dev] daily kan-ban update 10oct2020

[Cole Poirier]

On Sun, Oct 11, 2020 at 2:13 PM Cole Poirier <colepoirier at gmail.com> wrote:
>
> On Sun, Oct 11, 2020 at 1:21 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > On 10/11/20, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> > > sim.py operational with this, below.
> >
> > i have sim.py operational but versa_ecp5.py is not.  i back-tracked to
> > mid-september and that will display one line of text on the serial
> > console then stop.
> >
> > with no JTAG i can't get in and test it, i'll need to get some jumper
> > wires or hack up the 20 pin connector that comes with an STLINKv2.
>
> Awesome, same here, though
> `/home/colepoirier/src/litex/litex/build/sim/core/sim.c:95 Could not
> find module jtagremote`, but it exists in the same directory?
> ```
> ./litex/litex/build/sim/core/modules/jtagremote
> ./litex/litex/build/sim/core/modules/jtagremote/jtagremote.c
> ```
> Yup, sim reaches here and then seems to freeze (not respond to 'q' or
> 'esc') maybe I didn't wait long enough?
> ```
> --============== Boot ==================--
> Booting from serial...
> Press Q or ESC to abort boot completely.
> sL5DdSMmkekro
> ```

Yup just didn't wait long enough:

```
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
```

Only thing is, when I type nothing happens, no text appears. Do I
remember you telling jacob that some SPI/serial setting needed to get
this to work?

Cole