[Libre-soc-dev] daily kan-ban update 10oct2020

[Luke Kenneth Casson Leighton]

sim.py operational with this, below.   after i'd worked out that i'd
not correctly connected up the clocks. sigh.

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index eec494af..383afa0d 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,8 +28,8 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
-                         nocore=True, # to help test coriolis2 ioring
-                         gpio=False, # for test purposes
+                         #nocore=True, # to help test coriolis2 ioring
+                         gpio=True, # for test purposes
                          debug="jtag", # set to jtag or dmi
                          units=units)