[Libre-soc-dev] daily kan-ban update 10oct2020

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sat, Oct 10, 2020 at 10:35 PM Cole Poirier <colepoirier at gmail.com> wrote:
>
> New, possibly more relevant error... from yosys this time. no idea how
> to go about trying to fix this.
>
> ```
> 4.6. Executing FLATTEN pass (flatten design).
> <suppressed ~52 debug messages>
> ERROR: Mismatch in directionality for cell port
> versa_ecp5.test_issuer.int_level_i: \main_testsoc_libresoc_interrupt
> <= \test_issuer.int_level_i

sigh.  this is the interrupts, after *specifically* telling litex
"it's an input" it marks it as an output.

l.