[Libre-soc-dev] daily kan-ban update 10oct2020

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sat, Oct 10, 2020 at 10:07 PM Cole Poirier <colepoirier at gmail.com> wrote:

> Wasn't clear on the chain, thank you for elucidating it for me, much
> easier to reason about now.

issuer_verilog.py generates verilog according to parameters.  copy to
litex libresoc directory.  sim.py, ls180.py, versa_ecp5.py all take
that (same) file, and according to libresoc/core.py "variants"
parameter (currently ls180, standard, standard32) do different "stuff"
with that "core" (libresoc.v).

the litex "stuff" needs different pins and different functions
therefore back in the core (issuer_verilog.py) you need different
options.

l.