[Libre-soc-dev] daily kan-ban update 10oct2020

[Cole Poirier]

On Sat, Oct 10, 2020 at 1:32 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Sat, Oct 10, 2020 at 9:22 PM Cole Poirier <colepoirier at gmail.com> wrote:
> >
> > I'm trying to execute ./soc/litex/florent/versa_ecp5.py --build and
> > getting a cryptic error about a missing port. Any idea what this might
> > be?
>
> have a look in issuer_verilog.py and also in issuer.py
>
> > ```
> > 4.4.3. Analyzing design hierarchy..
> > Top module:  \versa_ecp5
> > Used module:     \test_issuer
> > ERROR: Module `test_issuer' referenced in module `versa_ecp5' in cell
> > `test_issuer' does not have a port named 'gpio_wb__err'.
>
> no gpio wishbone port.

Ah right... thank you.

> you see in issuer_verilog.py, the option to enable "test_gpio"?  then

No such variable test_gpio, do you mean:

```
20     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
21                          imem_ifacetype='bare_wb',
22                          addr_wid=48,
23                          mask_wid=8,
24                          # must leave at 64
25                          reg_wid=64,
26                          # set to 32 for instruction-memory width=32
27                          imem_reg_wid=64,
28                          # set to 32 to make data wishbone bus 32-bit
29                          #wb_data_wid=32,
30                          xics=True,
31                          nocore=True, # to help test coriolis2 ioring
32                          gpio=False, # for test purposes
                              ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
33                          debug="jtag", # set to jtag or dmi
34                          units=units)
```

> in issuer.py "if gpio_en add wishbone port"?  guess what that does...

No such variable gpio_en in issuer.py, do you mean:

```
138         # GPIO test peripheral
139         if self.gpio:
140             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
```

Cole