Hi Luke,
I've been trying to successfully compile and run the litex-libre-soc
simulation for over a week and have consistently been getting the
following error from running `make run_sim`. Has the procedure for
doing this changed since the addition of ls180.py? If so can you
explain what I need to do differently, then I can update the Makefile?
Apologies for the pasting of the long error message, but this is the
minimum necessary context that I was able to determine.
```
/home/colepoirier/src/litex/litex/soc/software/bios/cmds/cmd_bios.c:
In function ‘crc_handler’:
/home/colepoirier/src/litex/litex/soc/software/bios/cmds/cmd_bios.c:110:30:
warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
printf("CRC32: %08x", crc32((unsigned char *)addr, length));
^
CC cmd_mem.o
CC cmd_boot.o
CC cmd_i2c.o
CC cmd_spiflash.o
CC cmd_litedram.o
CC cmd_liteeth.o
CC cmd_litesdcard.o
CC main.o
LD bios.elf
chmod -x bios.elf
OBJCOPY bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf
/home/colepoirier/src/build/sim/software/bios/../include/generated/regions.ld
powerpc64le-linux-gnu
ROM usage: 29.95KiB (46.79%)
RAM usage: 1.66KiB (0.65%)
make: Leaving directory '/home/colepoirier/src/build/sim/software/bios'
Traceback (most recent call last):
File "src/soc/litex/florent/sim.py", line 480, in <module>
main()
File "src/soc/litex/florent/sim.py", line 476, in main
trace_fst = 0)
File "/home/colepoirier/src/litex/litex/soc/integration/builder.py",
line 214, in build
vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
File "/home/colepoirier/src/litex/litex/soc/integration/soc.py",
line 1048, in build
return self.platform.build(self, *args, **kwargs)
File "/home/colepoirier/src/litex/litex/build/sim/platform.py", line
54, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/colepoirier/src/litex/litex/build/sim/verilator.py",
line 229, in build
_compile_sim(build_name, verbose)
File "/home/colepoirier/src/litex/litex/build/sim/verilator.py",
line 153, in _compile_sim
raise OSError("Subprocess failed with {}\n{}".format(p.returncode,
"\n".join(error_messages)))
OSError: Subprocess failed with 2
make: Entering directory '/home/colepoirier/src/build/sim/gateware'
mkdir -p modules
[snip]
%Error: /home/colepoirier/src/build/sim/gateware/sim.v:7719: Pin not
found: gpio_wb__err
%Error: Exiting due to 11 error(s)
%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal -O3 --cc
/home/colepoirier/src/soc/src/soc/litex/florent/libresoc/libresoc.v
--cc /home/colepoirier/src/build/sim/gateware/sim.v --top-module sim
--exe -DPRINTF_COND\=0 sim_init.cpp
/home/colepoirier/src/litex/litex/build/sim/core/veril.cpp modules.o
pads.o sim.o libdylib.o parse.o --top-module sim -CFLAGS -Wall\ -O0\
-ggdb\ \ \ -I/home/colepoirier/src/litex/litex/build/sim/core -LDFLAGS
-lpthread\ -Wl\,--no-as-needed\ -ljson-c\ -lm\ -lstdc\+\+\
-Wl\,--no-as-needed\ -ldl\ -levent --trace --unroll-count 256
--output-split 5000 --output-split-cfuncs 500 --output-split-ctrace
500 -Wno-BLKANDNBLK -Wno-WIDTH
make: *** [/home/colepoirier/src/litex/litex/build/sim/core/Makefile:37:
sim] Error 10
make: Leaving directory '/home/colepoirier/src/build/sim/gateware'
```
Cole