[Libre-soc-dev] question about LRU implementation

[whygee at f-cpu.org]

Hello,
I am doing some research about LRU strategies and circuits,
so my question is : can any of you explain the methods
used by (or intended for) the cache memories and the TLB
selection & eviction circuits ?

I'm probably only "scratching an itch" but I'm looking
at "sub-optimal yet still good" strategies that save gates
by selecting a victim in the one half of the least recently
used part of the cache, so it's some sort of "pseudo-LRU".
I have two or three angles of attack on this challenge
and I'd love to compare them to other established works.

Thanks !
yg