[Libre-soc-dev] New AMD GPU BW Enhancing Shared L1 Cache

[Luke Kenneth Casson Leighton]

On Tue, Oct 6, 2020 at 2:58 AM Cole Poirier <colepoirier at gmail.com> wrote:
>
> Came across this cool but very short (11 min) talk by the lead university
> researcher responsible for the bandwidth enhancing cache coherency design
> that should be in the forthcoming AMD GPUs. Cool idea. Reminds me slightly
> (even though not directly related) of LDSTCompUnit’s batching.

the idea appears to be to reconfigure L1 caches to be shared or
private depending on workload and thus reduce bandwidth pressure on
L2.

shared L1.  that'll be a bundle of fun.  it might be practical to do
by sharing access to individual *blocks* of the L1 SRAM (there are
currently 4 "ways".  if each "way" can be made shared that would do
the trick).

l.