[Libre-soc-dev] Litex-OPENTitan clarification

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Oct 3 02:40:32 BST 2020


On Sat, Oct 3, 2020 at 1:08 AM Cole Poirier <colepoirier at gmail.com> wrote:

> subsequent tape-out in 2021). There's a SystemVerilog IEEE compliant
> parser library in rust, so I was thinking I could work with Jacob on
> creating a tool that uses this to convert the parts we want from
> OPENTitan into our litex-replacement nmigen implementation. I suggest
> creating a sv2nmigen translator because doing this any other way than
> automated/auto-generated would be massively time-consuming (the
> project is >100K LOC).

what you mean this?
https://git.libre-soc.org/?p=sv2nmigen.git;a=tree

> Ideally, Jacob and I would work on this largely
> without 'bothering' you, as I wouldn't want to distract you from the
> priority of our 30 OCT code-freeze deadline. Also, this is assuming
> that Jacob is even interested in working on this... Brain still a tad
> melty so pardon the style of this email, but I think this is possibly
> a good idea... let me know what you think :)

whilst what the lowRISC team did is great, it reinforces the lesson
that i also learned from the BSV generator:

*templates are unreadable* and ultimately unmaintainable.

because they use code-fragments with substitution, you can't write a
parser (sv2nmigen) for the *pre-completed* fragments because they
don't comply with the verilog syntax.

the templates only comply with verilog.... *AFTER* they have been used
to create actual verilog.

thus, they are worse than useless to us: they're a massive hindrance,
because the entirety of OpenTITAN must be a dependency.

thus, therefore, we must become experts in modifying (forking)
OpenTITAN and become experts in OpenTITAN's verilog templating system
and become experts in OpenTITAN configuration.

the fact that it is exclusively targetted at RISC-V processors makes
it *even less* attractive.

so we'd have to:

* learn verilog
* learn OpenTITAN configuration
* modify OpenTITAN to understand OpenPOWER and XICS interrupts
* generate verilog
* convert that to nmigen (fully convert: not partial-convert)

how reliable and workable do you think that's going to be?

does it not sound more attractive to work in python, to create
something that is direct and along the lines of what _we_ need,
define, and control the direction of?

if the OpenTITAN / lowRISC team had consulted us, sought our input,
and looked for ways to collaborate, i would not be asking that
question.

l.



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