[Libre-soc-dev] Coloquinte legalizer failure

Sat Dec 5 13:34:24 GMT 2020

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Luke Kenneth Casson Leighton schreef op za 05-12-2020 om 12:43 [+0000]:
> 
> https://bugs.libre-soc.org/show_bug.cgi?id=502#c2
> 
> 
> ah!  ok, that wasn't clear that that meant it was the verilog model.
> 
> however to do even a "dummy" P&R a dummy (phantom) cell that can be
> placed is needed, isn't it?

Yes, but you should be able to design RTL without needing to do P&R.
As the SRAM block will likely be places manually best to discuss with
JP how to proceed with this.

> 
> > I think the main question is that you do the mapping to the real
> > block
> > already in (n)migen/litex using Instance or you try to do it in a
> > custom yosys script. The former does guarantee that you use the
> > right
> > interface but I don't know the impact on your simulation flow. The
> > latter may cause problems if the interface to the memory block
> > changes
> > in generated Verilog/ilang code.
> 
> i.e. doesn't match the interface.

So I assume you will go for usage of Instance in litex code ?
In which tool do you want to simulate it ?

greets,
Staf.