[Libre-soc-dev] Coloquinte legalizer failure

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sat, Dec 5, 2020 at 9:51 AM Staf Verhaegen <staf at fibraservi.eu> wrote:
>
> Luke Kenneth Casson Leighton schreef op za 05-12-2020 om 01:18 [+0000]:
> > On 12/5/20, Cole Poirier <colepoirier at gmail.com> wrote:
> > because part of the layout is under NDA *he cannot provide it to
> > us*,only to Jean-Paul, and Jean-Paul, also under NDA, cannot provide
> > iteither.
>
> You don't need the layout in order to be able to do the synthesis. You
> will get the Verilog model of the SRAM block so also the input and
> output signals of the block. I already gave the interface of the block
> in bug 502.

https://bugs.libre-soc.org/show_bug.cgi?id=502#c2

ah!  ok, that wasn't clear that that meant it was the verilog model.

however to do even a "dummy" P&R a dummy (phantom) cell that can be
placed is needed, isn't it?

> I think the main question is that you do the mapping to the real block
> already in (n)migen/litex using Instance or you try to do it in a
> custom yosys script. The former does guarantee that you use the right
> interface but I don't know the impact on your simulation flow. The
> latter may cause problems if the interface to the memory block changes
> in generated Verilog/ilang code.

i.e. doesn't match the interface.

thx staf.

l.