[Libre-soc-dev] Port flexlib to skywater pdk 130nm

[Cole Poirier]

On Friday, December 4, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On 12/5/20, Cole Poirier <colepoirier at gmail.com> wrote:
>
> if it is limited in scope to a maximum of 1 week, and around EUR 500,


Perfect.


> and, critically, you in no way ask questions that you expect either
> Staf or JP to answer (because they absolutely cannot), nor post them
> where they could be distracted, *and* you also do not distract me from
> helping them to do the core for the 180nm ASIC, then go for it.
>

Yes this was already my understanding and intention. It’s the reason I
asked to crate the bug report, so I can put updates there, where it should
not have any chance of distracting JP, or Staf, and you can ignore it
unless you wish to peruse it for updates on my progress.


> you should probably start from one of the much smaller examples such
> as the am2901 or adder because the turnaround time will be extremely
> fast.
>

Thank you that’s helpful.


> bottom line, do not deluge the list with a barrage of 5 to 10
> questions per email: this one you need to tackle almost entirely on
> your own and/or by going out to external resources.
>

This was my intention. See my above comments.


> > Can I create a bug
> > report for this?
>
> sure.
>

Will do tomorrow.

Cole