[Libre-soc-bugs] [Bug 979] Implement C-based Power ISA decoder compiler

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=979

--- Comment #15 from Dmitry Selyutin <ghostmansd at gmail.com> ---
I think you remember how binutils did these tricks, eh?

#define TO TBR + 1
#define DUI TO
#define SVme TO
#define SVG TO
#define TO_MASK (0x1f << 21)
  { 0x1f, 21, NULL, NULL, 0 },

  /* The UI field in a D form instruction.  */
#define UI TO + 1
  { 0xffff, 0, NULL, NULL, 0 },


I've updated the generation so that it's clear that the same entry may refer to
multiple possible operands.

    [0] = /* BO, SVG, SVme, TO */ {
        .assemble = svp64_operand_assemble,
        .disassemble = svp64_operand_disassemble,
        .fields = {6, 7, 8, 9, 10},
    },

The decision on whether two different operands are the same depends on two key
factors:
1. Is operand class (cf. insndb/core.py) the same?
2. If so, are it's fields the same?

We don't care about names, at all, other than for documentation purposes.

-- 
You are receiving this mail because:
You are on the CC list for the bug.