[Libre-soc-bugs] [Bug 979] Implement C-based Power ISA decoder compiler

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=979

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Dmitry Selyutin from comment #11)
> TL;DR: at this stage, this will likely heavily follow binutils. IIRC they
> hash PO.

makes sense.

> Detailed answer. At this stage, I will most likely avoid optimizing it. 

gooood.

(In reply to Dmitry Selyutin from comment #13)
> So, to summarize:
> 0. Only disassembly.

gooood.

> I don't promise assembly (it's even outside of the tasks description).

ohh yes very much so. i'm slightly surprised you mention it, i can't
see what use there would be: i believe cavatools might actually use
objdump/disasm in its console?

> 1. Vanilla 32-bit instructions, but only those we have in openpower-isa. 

yes absolutely.  this is a crucial first step (even in the
openpower-isa PowerDecoder / PowerDecoder2) the augmentation
from SVP64 is entirely separate.

i absolutely insisted that there be NO mixing or changing of
SVP64-Prefixed instruction encoding, precisely so that
the 32-bit decoder may be used as-is, later.

> 2. No SVP64 yet.

agreed. it is firmly out of scope but would be covered by the
separate task anyway. (at which point, using c++ classes and
operator-overloads (on registers in particular) will make
the transformation of RA-as-5-bit into RA-as-7-bit much MUCH
easier, but again this is definitely NOT part of this task).

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