[Libre-soc-bugs] [Bug 1177] revert unauthorized change to pseudocode language

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1177

--- Comment #20 from Jacob Lifshay <programmerjake at gmail.com> ---
Ok, I finally fixed all the issues caused by merging shriya_add_descriptions.

we're back to 6 test failures (same as before). The test failures are listed at
the end of this comment.

I also fixed sc and the previously-working tests for it, since SRR1 is
specified to have bits 33:36 set to 0, 42:43 set to LEV (always 0 for now), and
44:47 set to 0. SRR1[TRAP] is *not* set.

calling TRAP isn't really what sc's pseudo-code should be doing (v3.1B just
writes NIA and MSR directly), but I left that mostly un-modified, just passed
in None so it knows not to try to set SRR1[TRAP].

So, can I merge to master?

https://git.libre-soc.org/?p=openpower-isa.git;a=shortlog;h=aa32b6a5063f32306a8b7e34f4d7741ea58cb79d

commit aa32b6a5063f32306a8b7e34f4d7741ea58cb79d
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon Nov 6 20:54:52 2023 -0800

    misc fixes for fallout of copying insn inputs

commit d87097d170c563cb8a24856854ec8628b5fcb7e0
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon Nov 6 20:38:18 2023 -0800

    System Call Interrupts do *not* set SRR1[TRAP]

    See PowerISA v3.1B Book III 7.5.14

commit 5df2836830494706e1d1a39bdf2470b26b32154c
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon Nov 6 20:37:07 2023 -0800

    support TRAP being called without setting a trap_bit

commit d60bd9dca97512869b8a811086b7620904b6ffc5
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon Nov 6 20:54:05 2023 -0800

    only write outputs that have .ok == True

commit b347cc3e750a82b2a94154636f1f0e1347fc98d7
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon Nov 6 20:49:19 2023 -0800

    use create_full_args to generate insn arg list

commit 8710b3b496d1e38877ae6123e565c790359dc8a4
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon Nov 6 20:46:03 2023 -0800

    add SelectableInt.ok

commit e554bd3457831925ea4f307a258d8f3cf8083825
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon Nov 6 20:43:13 2023 -0800

    helper for one-source-of-truth for insn argument list for ISACaller and
parser

commit 837d3f162bf071dc21fb4c7a7517a520b9cc2ae8
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Mon Nov 6 20:41:11 2023 -0800

    copy_assign_rhs must retain subclasses of SelectableInt

commit 392744106fe2e7c59def9e19d81bfb711d94251e
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Sun Nov 5 18:14:29 2023 -0800

    log load/stores to InstrInOuts

commit 2e76c0cbf9ef1620c32a1b7c3ccdc1369366a5ef
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Wed Nov 1 18:36:10 2023 -0700

    format code

commit 34bdb3eba18e55c8620893aae235559919fd951a
Author: Jacob Lifshay <programmerjake at gmail.com>
Date:   Tue Oct 31 22:50:40 2023 -0700

    misc AST correctness fixes


Test Failures:
[case_2_rfid] SUBFAIL
src/openpower/decoder/isa/test_caller_trap.py::TrapTest::test
[7:sv.cmp/zz/ff=gt/m=r3] SUBFAIL
src/openpower/sv/trans/test_pysvp64dis.py::SVSTATETestCase::test_20_cmp
[0:sv.rldimi] SUBFAIL
src/openpower/sv/trans/test_pysvp64dis.py::SVSTATETestCase::test_36_extras_rldimi
[0:rldimi] SUBFAIL
src/openpower/sv/trans/test_pysvp64dis.py::SVSTATETestCase::test_37_extras_rldimi
[0:sv.rldimi.] SUBFAIL
src/openpower/sv/trans/test_pysvp64dis.py::SVSTATETestCase::test_36_extras_rldimi_
[case_sc] SUBFAIL
src/openpower/decoder/isa/test_caller_syscall.py::TestSysCall::test
= 6 failed, 461 passed, 75 skipped, 19 xfailed, 822 warnings in 403.70s
(0:06:43) =

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