[Libre-soc-bugs] [Bug 1146] use separate computer instead of ddr3 for fpga memory interface for now

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1146

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #1)
> or, nuts to it: much simpler protocols barely above what wishbone
> is can also be written. at some point we do need an inter-memory
> protocol, to connect FPGAs together. this would be a step in that
> direction.

the main issue is things like the RPi don't speak HyperRAM or wishbone, so
using a protocol they already support is much better.

After doing some research, the RPi 4B apparently supports SPI (master only
afaict) at 125MHz divided by any power of two (250MHz divided by any even
number from 2 to 65536 but only powers of two work or something), so we could
have our FPGA act as a simple SPI slave and the RPi can just repeatedly read
the address to access and do the memory read/write as needed. If we do a good
job wiring it up (twisted pair and termination resistors), we could probably
get it to work at >10MHz (so like 1MB/s)

in any case, we will need the FPGA to wait for the computer to respond since it
may be busy servicing some interrupt or switched contexts or something. This is
another major problem with trying to talk to another computer using the
HyperRAM protocol -- iirc HyperRAM has no way to indicate the RAM isn't ready
yet.

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